1. Technical Field
This disclosure relates to semiconductor memory devices doped with Sb, Ga, or Bi and methods of manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices are developed with a focus on increasing information storage capacity and the speeds at which information is recorded and erased. Such a semiconductor memory device includes a large number of unit memory cells circuitally connected to one another.
Each unit cell of a semiconductor memory device such as a dynamic random access memory (DRAM) DRAM includes a transistor and a capacitor. The DRAM is a volatile memory device that can quickly process accesses but has a short retention time for a stored signal.
A representative example of a volatile memory device is a flash memory. Various other types of volatile memory devices such as silicon-nitride-oxide semiconductor (SNOS) memory devices, MRAMs, PRAMs, and the like have been developed. Flash memory devices, SNOS memory devices, and floating gate type memory devices commonly use materials having high dielectric constants (high-k). For purposes of this disclosure, a high-k material may be defined as one having a dielectric constant greater than about 3.9, which is the dielectric constant of SiO2.
FIGS. 1A and 1B are sectional diagrams illustrating a process of manufacturing a conventional SNOS memory device having a high-k. Referring to FIG. 1A, a tunneling oxide layer 13, a charge-trap layer 14, a blocking oxide layer 15, and a gate electrode layer 16 are sequentially formed on a semiconductor substrate 11. The tunneling oxide layer 13 may be formed of SiO2 to a thickness of about 30 Å, the charge-trap layer 14 may be formed of HfO2, and the blocking oxide layer 15 may be formed of Al2O3 to a thickness of 100 Å.
Next, both sides of each of the tunneling oxide layer 13, the charge-trap layer 14, the blocking oxide layer 15, and the gate electrode layer 16 are removed to form a gate. As a result, upper surfaces of the semiconductor substrate 11 are exposed on both sides of the gate.
Referring to FIG. 1B, the upper surfaces of the semiconductor substrate 11 to both sides of the gate are doped with a dopant, for example, boron (B) or phosphorous (P), using an ion implantation method. Here, the dopant is selected depending on a doping type of the semiconductor substrate 11. In other words, if the semiconductor substrate 11 is an n-type substrate, first and second dopant areas 12a and 12b are implanted with a material belonging to Group III so as to be doped with a p-type dopant. If the semiconductor substrate 11 is a p-type substrate, the first and second dopant areas 12a and 12b are implanted with a material belonging to Group V so as to be doped with an n-type dopant.
After the semiconductor substrate 11 is implanted with the dopant as shown in FIG. 1B, an annealing process is performed to activate the first and second dopant areas 12a and 12b as shown in FIG. 1B. For this purpose, the first and second dopant areas 12a and 12b are heated at a high temperature between about 900° C. and 1000° C. Once the first and second dopant areas 12a and 12b are activated by such a high temperature annealing process, the first and second dopant areas 12a and 12b may be useful in the semiconductor memory device.
However, the above-described high temperature annealing process may cause a high-k material that is used in a gate structure of a semiconductor memory device to be crystallized. In general, when the high-k material is amorphous in an initial deposition state, the high-k material must be insulated from the gate electrode layer 16 during an operation of the semiconductor memory device. However, when a material for the blocking oxide layer 15 is crystallized through the high temperature annealing process, a leakage current may be generated through a grain boundary area and may have a negative impact on the characteristics of the semiconductor memory device.
For example, FIGS. 2A and 2B illustrate characteristics of the memory devices shown in FIGS. 1A-1C that are manufactured with the high temperature annealing process described above.
FIG. 2A illustrates current-voltage (I-V) characteristics of conventional semiconductor memory devices that are annealed at temperatures of 700° C., 800° C., and 900° C. under an oxygen atmosphere. Referring to FIG. 2A, as a voltage approaches 0V, an intensity of a current is gradually reduced. However, the intensity of the current still approaches a value that is greater than zero. In particular, when the semiconductor memory device is annealed at a higher temperature of 900° C., the intensity of the current has a greater value.
FIG. 2B is a graph illustrating an X-ray diffraction (XRD) measured after the semiconductor memory device manufactured according to the process described with reference to FIGS. 1A and 1B is annealed at temperatures of 700° C., 800° C., 900° C., 950° C., and 1000° C. Referring to FIG. 2B, it can be seen that as an annealing temperature is increased, an Al2O3 peak becomes prominent at about 68°. This peak indicates that crystallization has occurred. In other words, as the annealing temperature increases, crystallization easily occurs.
FIG. 2C is a graph illustrating a retention characteristic of the semiconductor memory device manufactured according to the process described with reference to FIGS. 1A and 1B with respect to the annealing temperature. The semiconductor memory device has a high retention value less than or equal to “0.2” at the annealing temperature of 800° C. or less but a low retention value at the annealing temperature of 900° C.
Accordingly, the crystallization of a high-k material caused by a high temperature annealing process has a negative impact on the characteristics of conventional semiconductor memory devices such as those described above.
Embodiments of the invention address these and other disadvantages of the conventional art.